1. Field of the Invention
The present invention relates to a method for manufacturing a CMOS semiconductor device. More particularly, the present invention relates to a method for manufacturing a CMOS semiconductor device having a p type gate and an n type gate (dual gates) on a single semiconductor substrate.
2. Related Arts
A conventional method for manufacturing a CMOS semiconductor device having dual gates is shown in FIG. 2(a) to FIG. 2(c).
A device isolation region 32 is formed in a silicon substrate 31. Then, an NMOS transistor formation region 33 which is to become an NMOS region and a PMOS transistor formation region 34 which is to become a PMOS region are formed in the silicon substrate 31. Next, a gate insulating film 35 is formed on the surface of both the NMOS transistor formation region 33 and the PMOS transistor formation region 34. Then, a polysilicon film 36 is deposited on the entire surface of the silicon substrate 31(FIG. 2(a)).
A resist mask 37a is formed on the polysilicon film 36 so as to cover the PMOS transistor formation region 34. Next, n type impurity ions are implanted at a high concentration into the polysilicon film 36 in exposed state to form a high concentration n type polysilicon film 38 on the NMOS transistor formation region 33 (FIG. 2(b)).
The resist mask 37a is removed. Then, a resist mask 37b is formed on the n type polysilicon film 38 so as to cover the NMOS transistor formation region 33. Then, p type impurity ions are implanted at a high concentration into the polysilicon film 36 in exposed state to form a high concentration p type polysilicon film 39 on the PMOS transistor formation region 34 (FIG. 2(c)).
The resist mask 37b is removed. Next, a thermal-treatment is conducted in order to uniformize the impurity concentration in both of the n type polysilicon film 38 and the p type polysilicon film 39. A resist film is formed on the entire surface of the silicon substrate Then, a resist mask 37c is formed by patterning the resist film. Both the n type polysilicon film 38 and the p type polysilicon film 39 are etched with the resist mask 37c used as a mask, whereby an n type gate electrode 40 is formed on the NMOS transistor formation region 33 and a p type gate electrode 41 is formed on the PMOS transistor formation region 34.
Generally, an etching rate of the high concentration n type polysilicon film 38 and that of the high concentration p type polysilicon film 39 are different. Therefore, if the n type polysilicon film 38 is etched simultaneously with the p type polysilicon film 39 in a step for forming the gate electrodes, the n type polysilicon film 38 having a larger etching rate is completely etched and besides, the silicon substrate 31 of the NMOS transistor formation region 33 is over-etched, thereby causing a rough surface on the substrate as shown in FIG. 3(a). On the other hand, if the p type polysilicon film 39 is etched simultaneously with the n type polysilicon film 38 in a step for forming the gate electrodes, the p type polysilicon film 39 having a smaller etching rate is not fully etched, as shown in FIG. 3(b), thereby causing a problem such as a short-circuit.
The thinner a gate oxide film becomes in accordance with the size reduction of LSI, the bigger the above-mentioned problem becomes. Moreover, this problem can be a cause of extremely decreasing a process precision and reliability of the transistor.
To avoid this problem, a method is considered, which involves conducting an etching of the n type polysilicon film 38 and of the p type polysilicon film 39 separately.
However, in accordance with this method, another alignment process for forming a photo-resist mask is necessary. Accordingly, there arise problems such as lower productivity and higher production costs.